Seminar in NIISI RAS: 65 nm in outer space

January 30 NIISI Sciences held an internal seminar on "Issues of applicability 65nm CMOS VLSI under the impact of space environment." 

 

Employees NIISI RAS (Gorbunov, MS, etc.) reported on the results of research on the development of a test chip on 65nm technology. Employees of "ENGOs SPELS" were invited to the workshop participants as a part of the testing and interpretation of experimental results.

Of JSC "ENGOs SPELS" participated A.G.Petrov, A.B.Boruzdina and A.V.Ulanova. Boruzdina Anna B. gave a brief report on the subject: "Features of the tests of memory chips for resistance to individual nuclear particles taking into account the effect of multiple failures."

Plan report NIISI Sciences, as well as links to download the presentations are included below.

Briefly about the essence of the work. NIISI Academy of Sciences has developed a library of components for this technology and produced by a foreign factory TSMC test chip. In the crystal structure of the test is 4 blocks of memory (6-transistor memory cell, 6-transistor memory cell with security rings, various implementations DICE memory cells), a ring oscillator on IO, various options schemes majorization. It is worth noting that NIISI Sciences received a certificate as the first company in Russia to order the production of 65nm TSMC. The test blocks are kept to the level of performance of the dose exposure 1.2Mrad, the leakage current up to 5 times for a block of memory on the basis of 6T without guard rings for the remaining blocks the growth of the leakage current does not exceed 10%. The test results of the effect HCP and protons showed no effects thyristor in the range up to 60MeV LET * sm2/mg and was observed only in the unit cell without 6T guard rings only at elevated temperatures when tested on a xenon; observed failures, and multiple failures proportion is 50 % of the total number of failures. Some blocks multiple failures reaches 10 downed cells from a single particle. We draw the attention of developers of equipment that the problem of multiple failures that is parried by standard codes such as ECC (single correction, double error detection) increases with a decrease in chip design rules.

As a result of the work proved possible in principle to create a high-performance radiation-resistant sboeustoychivyh VLSI 65nm.

Also NIISI Sciences has launched a test chip on 65nm processor units, to the test of "ENGOs SPELS" he is expected at the end of the year (the crystal will be performed by Flip-Chip).

We hope that in the near future, the domestic electronics will be able to get rid of the dependence of the U.S. radiation resistant equipment.


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