Digital Frequency Counter

A digital frequency counter (DFC) is used for building, testing and designing analogue and digital circuits, li can also be used for measuring the frequency of any periodic waveform.

The fundamental operation is shown in the block diagram in Fig. 1.

The cost of a DFC is largely governed by the number of digits in its display and the maximum input frequency it can handle. An inexpensive instrument would typically offer a 4-digit display. This frequency counter* incorporating all the features, is comparatively cheaper.

A DFC normally has several measuring ranges. It is possible to add a few digits to the display by a method known as ‘over ranging’.

Block diagram

A clock oscillator circuit generates approximately 100 Hz signal whose frequency is divided by the divider network. At the output of the divider 11 Hz signal is obtained. This frequency has 1-sec. time period. The 1-sec. pulse is applied to the AND gate. Therefore, the unknown signal is passed through the AND gale for 1 sec. and the waveform frequency or the number of pulses per second are counted by the counter. The frequency is displayed on the 7-segment LEDs with the help of a digital panel meter.

The unknown input frequency should be a perfect square wave. For (his, we use the schmitt trigger which converts any waveform into a square wave. This unknown input signal must not be greater than 4V. If the input signal is very low (millivolts) it should be amplified with the help of an amplifier before being fed to the schmitt trigger circuit.

The circuit

IC 555 is used to generate the clock frequency and the output frequency at pin 3 is given to pin 1 of 7490, i.e. IC2.

IC2,1(3 and IC4 use decade counters. The frequency at pin 12 of IC2 is the ENABLE gate signals, This time period is used for measuring the frequency of input signals.

The output at pin 12 of IC2 is connected to pin 1 of ICS by the DPDT switch SI. The IC5 is a dual J-K flip-flop with separate sets, clears and clocks. If 1 Hz square wave is used to drive the J-K flip-flop, i is out put G will be 0.5 Hz square wave.

The output 0 will be high for exactly 1 sec. and low for 1 sec., and it will thus be used for the ENAF3LF, gate signal. Note that 10Hz square wave will generate a 0.1-sec. gale and the 0,1 Hz square wave will generate a 10-sec. gale enable time.

When the J-K flip-flop is toggle high, measurement period starts. Now the unknown input signal posses through the count gale IC7 (7408) and advances the counter. Assume th:it the counter Is at 0000. At the end of the gale lime, say 1 sec., The counter reading is the final frequency. Positive transition of Q of ICS triggers the monosyllable multivibrator 1C6 (74121) one-shot, Therefore, at pin 6 of 1C6, a positive RESET pulse appears. This pulse is used to reset the counters. Now to latch the exactly 10 Hz. At pin 12oflC3and IC4 the frequency is 1 Hz and 0.1 Hz respectively. Hence, the time period of generating pulse at pin 12 ofIC2* IC3 and IC4 is 0.1 sec., 1 sec. and 10 sec. respectively. These pulses are used for contents of counter, a negative pulse is required. Hence, the output 0 of 1C5 is used for this purpose. The input signal can be of any form. To convert these signals into square wave, schmitt trigger is used. The schmitt trigger is built around timer 7555. A square wave of equivalent frequency of input signal is received at pin 3 of IC8 and is fed into AND gate. To count the frequency, AND gate is used as count gate which passes the frequency for the selected gate time. Ihe gate time is selected by switch SI.

The display circuit is built around the National Semiconductor IC 74C926. It has a 4-digit counter with multiplexed 7-segment output drivers, internal output latch and a source driver for the display.

The CMOS 1C is an 18-pin, dual-inline package. It has four decade counters, latches and reset input. It consists of an eternal multiplexing circuitry with four multiplexed outputs. This multiplexed circuit has its own free-running oscillator.

A carry out pin, i.e. pin 14, is also available for cascading the counter. I lence we can also increase the range of this frequency counter. With the help of this pin, we can increase the number of digits from four to eight. The internal counter of the 1C advances on each negative edge of the clock pulse, which is received at pin 12 by IC7. A high signal on display SELECT; i.e. pin 6, through 1-kilohm resistor selects the number in the counter to be displayed. Low signal on latch enable input latches the count at the output. ‘Hie display used for this chip is 7-segment common-cathode type. IC 74C926’s range Of supply is +3 V to +6V with high noise immunity (noise swings IV).

The signal generated by IC6 is fed to the reset terminal of 74926 IC. This reset pulse has an arbitrary width of lys. set by capacitor C3 and preset VRl timing components. The end of the reset pulse is the end of one measurement period.

If we select one second gate time, at that instant the decimal point will be at the right of the third digit (D1S1) and the counter will be capable of counting up to 9999 Hz full scale. With the help of this counter we can measure up to 10 kHz by selecting different gate timings, and the accuracy is compatible with that of the counter.

You can set the reset pulse by a suitable combination of capacitor C3 and preset VR2, as shown in Fig.2.

Assembly, testing and calibration

This project is easy to assemble on a general-purpose or the suggested PCB. All The ICS should be mounted on IC sockets and soldered carefully. All components should be checked before assembly. After completing the assembly, the power supply should be checked. It should not be greater than 5 volts regulated. Also check whether IC 555 is generating clock pulses or not. The output at the counters should also be examined.

For calibration of the circuit give known input frequency at the input terminal and set it at display with the tie Ip of presets VR1 and VR2. When it displays the input frequency correctly, the calibration is complete. Now the frequency counter is ready for measuring any unknown frequency of an input signal. All the above circuits, including the display, may be enclosed in a metal cabinet. For better results, the cabinet should be shorted to ground.

Conclusion

A DFC is not difficult to use, but you need to be careful about the choice of the test-point when testing LC oscillator, especially the high frequency types. In general, it is best to choose a low impedance part of the circuit and, as far as possible, avoid taking the signal directly.

Remember there will be a certain amount of capacitance in the test leads, and the DFC itself will have a small amount of input capacitance. This can significantly reduce the operating frequency of the circuit and, in an extreme case, damp the oscillator to the point where it will cease to function.

Like this post? Please share to your friends: